A 1-bit Synchronization Algorithm for a Reduced Complexity Energy Detection UWB Receiver

This work investigates the possibility of performing synchronization in a reduced complexity Energy Detection receiver. A new receiver scheme employing a single comparator only is defined and the related synchronization algorithm is presented. The possibility of synchronizing has been analyzed both for an idealized Dirac Delta input signal and for realistic UWB signals obtained through the TG4a channel model. The matlab simulations show that it is possible to obtain coarse synchronization using a simple maximum detection algorithm computed on collected energies for the ideal case of Dirac Delta pulses. For realistic UWB signals better synchronization performances are possible by employing a searchback algorithm. Due to the low complexity of the receiver scheme, the synchronization algorithm requires a long locking time

An effective AMS Top-Down Methodology Applied to the Design of a Mixed-SignalUWB System-on-Chip

The design of Ultra Wideband (UWB) mixed-signal SoC for localization applications in wireless personal area networks is currently investigated by several researchers. The complexity of the design claims for effective top-down methodologies. We propose a layered approach based on VHDL-AMS for the first design stages and on an intelligent use of a circuit-level simulator for the transistor-level phase. We apply the latter just to one block at a time and wrap it within the system-level VHDL-AMS description. This method allows to capture the impact of circuit-level design choices and non-idealities on system performance. To demonstrate the effectiveness of the methodology we show how the refinement of the design affects specific UWB system parameters such as bit-error rate and localization estimations

A Low-power CMOS 2-PPM Demodulator for Energy Detection IR-UWB Receivers

This paper presents an integrated 2-PPM CMOS demodulator for non-coherent energy detection receivers which inherently provides analog-to-digital conversion. The device, called Bi-phase integrator, employs an open loop Gm - C integrator loaded with a switched capacitor network. The circuit has been simulated in a mixed-mode UMC 0.18mum technology and its performance figures are obtained through a mixed-signal simulation environment developed with the aid of ADVanceMS (ADMS, mentor graphics). Bit-error-rate simulations show that the circuit performance is about the same of an ideal energy detection receiver employing infinite quantization resolution. In addition, the simulations show that the circuit provides a complete offset rejection. Thanks to its low power consumption (1 mW during demodulation), its application is appealing for portable devices which aim at very low-power consumption

A multiprocessor based packet-switch: performance analysis of the communication infrastructure

The intra-chip communication infrastructures are receiving always more attention since they are becoming a crucial part in the development of current SoCs. Due to the high availability of pre-characterized hard-IP, the complexity of the design is moving toward global interconnections which are introducing always more constraints at each technology node. Power consumption, timing closure, bandwidth requirements, time to market, are some of the factors that are leading to the proposal of new solutions for next generation multi-million SoCs. The need of high programmable systems and the high gate-count availability is moving always more attention on multiprocessors systems (MP-SoC) and so an adequate solution must be found for the communication infrastructure. One of the most promising technologies is the Network-On-Chip (NoC) architecture, which seems to better fit with the new demanding complexity of such systems. Before starting to develop new solutions, it is crucial to fully understand if and when current bus architectures introduce strong limitations in the development of high speed systems. This article describes a case study of a multiprocessor based ethernet packet-switch application with a shared-bus communication infrastructure. This system aims to depict all the bottlenecks which a shared-bus introduces under heavy load. What emerges from this analysis is that, as expected, a shared-bus is not scalable and it strongly limits whole system performances. These results strengthen the hypothesis that new communication architectures (like the NoC) must be found

An Electromigration and Thermal Model of Power Wires for a Priori High-Level Reliability Prediction

In this paper, a simple power-distribution electrothermal model including the interconnect self-heating is used together with a statistical model of average and rms currents of functional blocks and a high-level model of fanout distribution and interconnect wirelength. Following the 2001 SIA roadmap projections, we are able to predict a priori that the minimum width that satisfies the electromigration constraints does not scale like the minimum metal pitch in future technology nodes. As a consequence, the percentage of chip area covered by power lines is expected to increase at the expense of wiring resources unless proper countermeasures are taken. Some possible solutions are proposed in the paper

A case study for NoC based homogeneous MPSoC architectures

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processo

Experimental Analysis of Open-Circuit Voltage Hysteresis in Lithium-Iron-Phosphate Batteries

This paper aims at investigating and modelling the hysteresis in the relationship between state-of-charge and open-circuit voltage of lithium-iron-phosphate batteries. A first-order charge relaxation equation was used to describe the hysteresis dynamics. This equation was translated into a voltage-controlled voltage source and included within an equivalent electric circuit of the battery used in online state-of-charge estimators. The effectiveness of the obtained battery model was verified comparing simulated and experimental data

Comparison of State and Parameter Estimators for Electric Vehicle Batteries

A Battery Management System (BMS) is needed to ensure a safe and effective operation of a Lithium-ion battery, especially in electric vehicle applications. An important function of a BMS is the reliable estimation of the battery state in a wide range of operating conditions. To this end, a BMS often uses an equivalent electrical model of the battery. Such a model is computationally affordable and can reproduce the battery behaviour in an accurate way, assuming that the model parameters are updated with the actual operating condition of the battery, namely its state-of-charge, temperature and ageing state. This paper compares the performance of two battery state and parameter estimation techniques, i.e., the Extended Kalman Filter and the classic Least Squares method in combination with the Mix algorithm. Compared to previous ones, this work focuses on the concurrent estimation of battery state and parameters using experimental data, measured on a Lithium-ion cell subject to a current profile significant for an electric vehicle application